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Table of Content
LCD SEGMENT / COMMON DRIVER WITH CONTROLLER ..................................................................................1 FEATURES ................................................................................................................................................................1 ORDERING INFORMATION......................................................................................................................................2 BLOCK DIAGRAM.....................................................................................................................................................3 TAB PAD ARRAGEMENT (SSD1851T PIN ASSIGNMENT) ..................................................................................4 COF PAD ARRAGEMENT (SSD1851U PIN ASSIGNMENT) ...................................................................................5 DIE PAD ARRAGEMENT (SSD1850Z DIE PIN ASSIGNMENT) ..............................................................................6 DIE PAD ARRANGEMENT (SSD1851Z DIE PIN ASSIGNMENT) ...........................................................................7 PIN DESCRIPTIONS................................................................................................................................................11
RES ....................................................................................................................................................................11 PS0, PS1 .............................................................................................................................................................11 CS .......................................................................................................................................................................11 D/ C .....................................................................................................................................................................11 R/W ( WR ) ..........................................................................................................................................................11 D0-D7 ..................................................................................................................................................................11 INTRS..................................................................................................................................................................11 REF .....................................................................................................................................................................11 VDD .....................................................................................................................................................................11 VSS .....................................................................................................................................................................12 VCI.......................................................................................................................................................................12 VCC .....................................................................................................................................................................12 C1P, C2P, C3P, C4P, C5P, C1N and C2N ........................................................................................................12 VL6 ......................................................................................................................................................................12
This document contains information on a new product. Specification and information herein are subject to change without notice. Copyright 2003 SOLOMON Systech Limited Rev 1.2 01/2003
VR........................................................................................................................................................................12 VEXT ...................................................................................................................................................................12 VL5, VL4, VL3 and VL2......................................................................................................................................12 COM0 - COM79...................................................................................................................................................12 ICONS .................................................................................................................................................................12 SEG0 - SEG127 ..................................................................................................................................................13 S5150 ..................................................................................................................................................................13 CL ........................................................................................................................................................................13 N/C ......................................................................................................................................................................13 FUNCTIONAL BLOCK DESCRIPTIONS ................................................................................................................14 Command Decoder and Command Interface .................................................................................................14 MPU Parallel 6800-series Interface ..................................................................................................................14 MPU Parallel 8080-series interface ..................................................................................................................14 MPU Serial 4-wire Interface ..............................................................................................................................15 MPU Serial 3-wire Interface ..............................................................................................................................15 Modes of operation ...........................................................................................................................................15 Graphic Display Data RAM (GDDRAM) ...........................................................................................................15 Oscillator Circuit................................................................................................................................................18 LCD Driving Voltage Generator and Regulator ..............................................................................................18 193 / 209 Bit Latch .............................................................................................................................................19 Level Selector ....................................................................................................................................................19 HV Buffer Cell (Level Shifter) ...........................................................................................................................19 Reset Circuit ......................................................................................................................................................20 LCD Panel Driving Waveform...........................................................................................................................21 COMMAND TABLE ............................................................................................................................................22 Extended Command Table ...............................................................................................................................25 Frame Frequency Default Setting ....................................................................................................................26
This document contains information on a new product. Specification and information herein are subject to change without notice. Copyright 2003 SOLOMON Systech Limited Rev 1.2 01/2003
Read Status Byte ...............................................................................................................................................27 Data Read / Write ...............................................................................................................................................27 Address Increment Table (Automatic) ............................................................................................................27 Commands Required for R/W ( WR ) Actions on RAM ..................................................................................27 COMMAND DESCRIPTIONS ..................................................................................................................................28 Set Display On/Off .............................................................................................................................................28 Set Display Start Line .......................................................................................................................................28 Set Page Address ..............................................................................................................................................28 Set Lower Column Address .............................................................................................................................28 Set Segment Re-map ........................................................................................................................................28 Set Normal/Inverse Display ..............................................................................................................................28 Set Entire Display On/Off..................................................................................................................................28 Set LCD Bias ......................................................................................................................................................28 Software Reset...................................................................................................................................................28 Set COM Output Scan Direction ......................................................................................................................28 Set Power Control Register..............................................................................................................................29 Set Internal Regulator Resistors Ratio ...........................................................................................................29 Set Contrast Control Register..........................................................................................................................29 Set Display Offset..............................................................................................................................................29 Set Multiplex Ratio ............................................................................................................................................30 Set Power Save Mode .......................................................................................................................................30 Exit Power Save Mode ......................................................................................................................................30 Set N-line Inversion ...........................................................................................................................................30 Exit N-line Inversion ..........................................................................................................................................30 Set DC-DC Converter Factor ............................................................................................................................30 Set Icon Enable..................................................................................................................................................30 Start Internal Oscillator.....................................................................................................................................30
This document contains information on a new product. Specification and information herein are subject to change without notice. Copyright 2003 SOLOMON Systech Limited Rev 1.2 01/2003
Set Display Data Length ...................................................................................................................................30 Set Gray Scale Mode (White/Light Gray/Dark Gray/Black) ...........................................................................30 Set PWM and FRC .............................................................................................................................................31 Set Test Mode ....................................................................................................................................................31 Status Register Read ........................................................................................................................................31 EXTENDED COMMANDS ..................................................................................................................................31 Set VL6 noise reduction ...................................................................................................................................31 Set Temperature Coefficient (TC) Value..........................................................................................................31 Select Oscillator Source ...................................................................................................................................31 Oscillator adjustment........................................................................................................................................31 Lock/Unlock Interface .......................................................................................................................................31 MAXIMUM RATINGS ...............................................................................................................................................32 ELECTRICAL CHARACTERISTICS .......................................................................................................................32 AC ELECTRICAL CHARACTERISTICS .................................................................................................................34 APPLICATION CIRCUIT..........................................................................................................................................41 Application Circuit: DC-DC Converter Circuit Configuration .......................................................................42 Application Circuit: Regulator Circuit and Bias Divider Circuit ...................................................................43 Internal Regulator and Bias Divider ................................................................................................................43 External Regulator and Internal Bias Divider .................................................................................................43 External Regulator Bias Divider.......................................................................................................................43 OTP Programming Circuit and Sequence.......................................................................................................44 Flow Chart of OTP Program .............................................................................................................................45 OTP Example program......................................................................................................................................46 SSD1851T TAB PACKAGE DIMENSION .........................................................................................................47 SSD1851U COF PACKAGE DIMENSION ........................................................................................................50
This document contains information on a new product. Specification and information herein are subject to change without notice. Copyright 2003 SOLOMON Systech Limited Rev 1.2 01/2003
SOLOMON SYSTECH LIMITED SEMICONDUCTOR TECHNICAL DATA
SSD1850/51
Advance Information
CMOS
LCD Segment / Common Driver with Controller
SSD1850/51 is a single-chip CMOS LCD driver with controller for liquid crystal dot-matrix graphic display system. SSD1850 consists of 194 high voltage driving output pins for driving 128 Segments and 64 Commons and 1 icon line. SSD1851 consists of 210 high voltage driving output pins for driving 128 Segments and 80 Commons and 1 icon line. SSD1850/51 display data directly from their internal 128x65x2 / 128x81x2 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through hardware selectable 6800/8080-series compatible Parallel Interface or 3/4 wires Serial Peripheral Interface. SSD1850/51 embeds a DC-DC Converter, a LCD Voltage Regulator, an On-Chip Bias Divider and an On-Chip Oscillator which reduce the number of external components. With the special design on minimizing power consumption and die/package layout, SSD1850/51 is suitable for any portable batterydriven applications requiring long operation period and compact size.
FEATURES
128x64/80 + 1 icon line, 4 gray-levels Graphic Display Programmable Multiplex ratio [16Mux - 65Mux/81Mux] Single Supply Operation, 1.8 V - 3.3V Low Current Sleep Mode(<1.0 uA) On-Chip Voltage Generator / External Power Supply Software selectable 2X / 3X / 4X / 5X / 6X On-Chip DC-DC Converter On-Chip Oscillator On-Chip Bias Dividers Programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10 bias ratio Maximum +15.0V LCD Driving Output Voltage Hardware pin selectable for 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, 3-wire Serial Peripheral Interface or 4-wire Serial Peripheral Interface On-Chip 128x65x2 / 128x81x2 Graphic Display Data RAM Re-mapping of Row and Column Drivers Vertical Scrolling Display Offset Control 64 Level Internal Contrast Control External Contrast Control Maximum 15MHz SPI or 10MHz PPI (8 bit) operation Selectable LCD Driving Voltage Temperature Coefficients (2 settings) Available in Gold Bump Die, Standard TAB (Tape Automated Bonding) Package and COF (Chip On Foil)
This document contains information on a new product. Specification and information herein are subject to change without notice. Copyright 2002 SOLOMON Systech Limited Rev 1.2 01/2003
ORDERING INFORMATION
Ordering Part Number SSD1850Z SSD1851Z SSD1851TR1 SSD1851U SEG 128 128 128 128 COM 64 + 1 80 + 1 80 + 1 80 + 1 Default Bias 1/9 1/10 1/10 1/10 Package Form Gold Bump Die Gold Bump Die TAB COF Reference
2
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
BLOCK DIAGRAM
ICONS ROW0 to ROW63 (SSD1850) ROW0 to ROW79 (SSD1851) SEG0 ~SEG127
HV Buffer Cell Level Shifter
Level Selector
VL6 VL5 VL4 VL3 VL2 VSS
LCD Driving Voltage Generator 2X/3X/4X/5X/ 6X DC/DC Converter, Voltage Regulator, Bias Divider, Contrast Control, Temperature Compensation
193 Bit Latch (SSD1850) 209 Bits Latch (SSD1851)
Display Timing Generator
VR V CC C1P C2P C3P C4P C5P C1N C2N REF INTRS V CI V EXT
CL
Oscillator
GDDRAM 128 x 65 x 2 Bits (SSD1850) 128 x 81 x 2 Bits (SSSD1851)
VSS VDD Command Decoder
Command Interface
Parallel / Serial Interface
RES# PS0 PS1 CS#
R/W
E
D/C
D7 D6
(SDA)(SCK)
D5
D4
D3
D2
D1 D0
(WR#)(RD#)
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
3
TAB PAD ARRAGEMENT (SSD1851T PIN ASSIGNMENT) (Copper View)
N/C 1 CL 2 VR 3 VL6 4 VL5 5 VL4 6 VL3 7 VL2 8 INTRS 9 C4P 10 C2N 11 C2P 12 C1P 13 C1N 14 C3P 15 C5P 16 VCC 17 VSS 18 VCI 19 VDD 20 D7 21 D6 22 D5 23 D4 24 D3 25 D2 26 D1 27 D0 28 E(RD#) 29 R/W(WR#)30 D/C 31 RES# 32 CS# 33 PS1 34 PS0 35 N/C 36
247 NC 246 NC 245 COM39 244 COM38 243 COM37
209 COM1 208 COM0 207 ICONS 206 SEG0 205 SEG1
81 SEG125 80 SEG126 79 SEG127 78 COM40 77 COM41
42 COM76 41 COM77 40 COM78 39 COM79 38 ICONS 37 N/C
Remarks: REF is connected to VDD VEXT is not connected
4
SSD1850/51 Series Rev 1.2 01/2003 SOLOMON
COF PAD ARRAGEMENT (SSD1851U PIN ASSIGNMENT)(Copper View)
COM41 COM40 SEG127 SEG126
N/C N/C ICONS COM79
Remarks:
REF is connected to VDD VEXT is not connected INTRS is connected to VDD VR is not connected Default Setting: PS0 and PS1 are connected to VDD (6800 Parallel Interface Mode)
5
GND VDD D7 D6 D5 D4 D3 D2 D1 D0 E R/W(WR#) D/C RES# CS# GND
COM38 COM39 N/C N/C
SEG2 SEG1 SEG0 ICONS COM0 COM1
SEG99 SE98 SEG97 SEG96
SEG55 SEG54 SEG53 SEG52
VSS VDD PS0 VDD PS1 VSS
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
DIE PAD ARRAGEMENT (SSD1850Z DIE PIN ASSIGNMENT)
N/C COM18 COM19 COM20 COM21
COM29 COM30 COM31 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
N/C
Center: 5508.0, 765.0
COM17 COM16 COM15 COM14 COM13 COM12 COM11
157 156 132 131
COM5 COM4 COM3 COM2 COM1 COM0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13
SEG112 SEG113 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM40 COM41 COM42 COM43 COM45 COM46 COM47 COM48 COM49 COM50
323 324
347
1
6
COM62 COM63 N/C N/C N/C N/C N/C N/C N/C N/C ICONS N/C N/C
NC
COM51 COM52 COM53 COM54 COM55
NC NC NC CL VSS VR VR VL6 VL6 VL6 VL5 VL5 VL5 VL4 VL4 VL4 VL3 VL3 VL3 VL2 VL2 VL2 VSS C4P C4P C4P C2N C2N C2N C2N C2P C2P C2P C1P C1P C1P C1N C1N C1N C1N C3P C3P C3P N/C N/C N/C VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCI VCI VCI VCI VDD VDD VDD D7 D7 D6 D6 D5 D4 D3 D2 D1 D0 VDD E(RD#) E(RD#) R/W(/WR#) R/W(/WR#) VSS D/C D/C D/C RES# VDD CS# CS# VSS PS1 VDD VSS PS0 VDD S5150 VSS N/C N/C N/C N/C N/C
X
Center (-5243.7, -522.3) Size: 78.5 x 78.5
X
Center (-5309.85, -522.3) Size: 78.5 x 78.5
Center: 5243.7, -522.3
Center: 5328.75, 84.3
18 m 75 m
18 m
X
X
75 m
(-5508.0, 765.0)
(5508.0, 765.0)
Note: 5. 6. 7. 8.
The gold bumps face up in this diagram. Coordinates reference to center of the chip. All dimensions and coordinates in um. All alignment keys do not contain gold bump. 12300um x 1960um 534um +/- 25 um Nominal 18 um < 3 um within die
X
Die Size: Die Thickness: Bump Height: Tolerance
Y
(0,0)
Center: -5508.0, 765.0
Center: -5309.85, 522.3
Center (5328.75, 84.3) Size: 78.5 x 78.5
SSD1850Z Die Pin Assignment DRAWING NOT SCALE
PIN #1
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
DIE PAD ARRANGEMENT (SSD1851Z DIE PIN ASSIGNMENT)
N/C COM18 COM19 COM20 COM21
COM38 COM39 N/C N/C
N/C
Center: 5508.0, 765.0
COM17 COM16 COM15 COM14 COM13 COM12 COM11
157 156 132 131
COM5 COM4 COM3 COM2 COM1 COM0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13
SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM32 COM33 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM56 COM57 COM58
323 324
347
1
COM78 COM79 ICONS N/C N/C
NC
COM59 COM60 COM61 COM62 COM63
NC NC NC CL VSS VR VR VL6 VL6 VL6 VL5 VL5 VL5 VL4 VL4 VL4 VL3 VL3 VL3 VL2 VL2 VL2 VSS C4P C4P C4P C2N C2N C2N C2N C2P C2P C2P C1P C1P C1P C1N C1N C1N C1N C3P C3P C3P C5P C5P C5P VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCI VCI VCI VCI VDD VDD VDD D7 D7 D6 D6 D5 D4 D3 D2 D1 D0 VDD E(RD#) E(RD#) R/W(/WR#) R/W(/WR#) VSS D/C D/C D/C RES# VDD CS# CS# VSS PS1 VDD VSS PS0 VDD S5150 VSS N/C N/C N/C N/C N/C
X
Center (-5243.7, -522.3) Size: 78.5 x 78.5
X
Center (-5309.85, -522.3) Size: 78.5 x 78.5
Center: 5243.7, -522.3
Center: 5328.75, 84.3
18 m 75 m
18 m
X
X
75 m
(-5508.0, 765.0)
(5508.0, 765.0)
Note: 1. 2. 3. 4.
The gold bumps face up in this diagram. Coordinates reference to center of the chip. All dimensions and coordinates in um. All alignment keys do not contain gold bump. 12300um x 1960um 534um +/- 25 um Nominal 18 um < 3 um within die
X
Die Size: Die Thickness: Bump Height: Tolerance
Y
(0,0)
Center: -5508.0, 765.0
Center: -5309.85, 522.3
Center (5328.75, 84.3) Size: 78.5 x 78.5
SSD1851Z Die Pin Assignment DRAWING NOT SCALE
PIN #1
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
7
Table 1 - SSD1850/51 Die Pad Coordinates
Pad #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SSD 1851
N/C N/C N/C N/C N/C VSS S5150 VDD PS0 VSS VDD PS1 VSS CS# CS# VDD RES# D/C D/C D/C VSS R/W (WR#) R/W (WR#) E(RD#) E(RD#) VDD D0 D1 D2 D3 D4 D5 D6 D6 D7 D7 VDD VDD VDD VCI VCI VCI VCI VSS VSS VSS VSS VSS VSS VSS
SSD 1850
N/C N/C N/C N/C N/C VSS S5150 VDD PS0 VSS VDD PS1 VSS CS# CS# VDD RES# D/C D/C D/C VSS R/W (WR#) R/W (WR#) E(RD#) E(RD#) VDD D0 D1 D2 D3 D4 D5 D6 D6 D7 D7 VDD VDD VDD VCI VCI VCI VCI VSS VSS VSS VSS VSS VSS VSS
X-pos
-5698.05 -5620.65 -5543.25 -5465.85 -5355.68 -5279.48 -5203.28 -5127.08 -5050.88 -4974.68 -4898.48 -4822.28 -4746.08 -4669.88 -4593.68 -4517.48 -4441.28 -4365.08 -4288.88 -4212.68 -4136.48
Y-pos
-830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85
Pad #
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
SSD 1851
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC C5P C5P C5P C3P C3P C3P C1N C1N C1N C1N C1P C1P C1P C2P C2P C2P C2N C2N C2N C2N C4P
SSD 1850
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC N/C N/C N/C C3P C3P C3P C1N C1N C1N C1N C1P C1P C1P C2P C2P C2P C2N C2N C2N C2N C4P
X-pos
-1687.2 -1611 -1534.8 -1458.6 -1382.4 -1306.2 -1230 -1153.8 -1077.6 -1001.4 -925.2 -849 -772.8 -696.6 -620.4 -544.2 -468 -391.8 -315.6 -239.4 -163.2 -87 -10.8 65.4 141.6 872.55 953.85 1035.15 1116.45 1197.75 1279.05 1360.35 1441.65 1522.95 1604.25 1685.55 1766.85 1848.15 1929.45 2066.25 2147.55 2228.85 2310.15 2391.45 2472.75 2554.05 2635.35 2716.65 2797.95 2934.75
Y-pos
-863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -863.55 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15
Pad #
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
SSD 1851
C4P C4P VSS REF VEXT VDD INTRS VSS VL2 VL2 VL2 VL3 VL3 VL3 VL4 VL4 VL4 VL5 VL5 VL5 VL6 VL6 VL6 VR VR VSS CL N/C N/C N/C N/C N/C N/C COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23
SSD 1850
C4P C4P VSS REF VEXT VDD INTRS VSS VL2 VL2 VL2 VL3 VL3 VL3 VL4 VL4 VL4 VL5 VL5 VL5 VL6 VL6 VL6 VR VR VSS CL N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23
X-pos
3016.05 3097.35 3173.55 3249.75 3366.45 3442.65 3518.85 3595.05 3671.25 3752.55 3833.85 3915.15 3996.45 4077.75 4159.05 4240.35 4321.65 4402.95 4484.25 4565.55 4646.85
Y-pos
-804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15
-4060.28 -830.85 -3984.08 -830.85 -3907.88 -3831.68 -3755.48 -3679.28 -3603.08 -3526.88 -3450.68 -3374.48 -3298.28 -3222.08 -3145.88 -3069.68 -2993.48 -2917.28 -2841.08 -2764.88 -2620.05 -2538.75 -2457.45 -2376.15 -2266.35 -2190.15 -2113.95 -2037.75 -1961.55 -1885.35 -1763.4 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -830.85 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -804.15 -863.55
4728.15 -804.15 4809.45 -804.15 4926.15 5002.35 5078.55 5154.75 5267.55 5344.95 5422.35 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 -804.15 -804.15 -804.15 -804.15 -830.85 -830.85 -830.85 -898.05 -665.25 -600.45 -535.65 -470.85 -406.05 -341.25 -276.45 -211.65 -146.85 -82.05 -17.25 47.55 112.35 177.15 241.95 306.75 371.55 436.35 501.15
8
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
Pad #
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
SSD 1851
COM22 COM21 COM20 COM19 COM18 N/C COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SSD 1850
COM22 COM21 COM20 COM19 COM18 N/C COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
X-pos
5974.20 5974.20 5974.20 5974.20 5974.20 5974.20 5346.00 5281.20 5216.40 5151.60 5086.80 5022.00 4957.20 4892.40 4827.60 4762.80 4698.00 4633.20 4568.40 4503.60 4438.80 4374.00 4309.20 4244.40 4179.60 4114.80 4050.00 3985.20 3920.40 3855.60 3790.80 3726.00 3661.20 3596.40 3531.60 3466.80 3402.00 3337.20 3272.40 3207.60 3142.80 3078.00 3013.20 2948.40 2883.60 2818.80 2754.00 2689.20 2624.40 2559.60
Y-pos
565.95 630.75 695.55 760.35 825.15 889.95 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55
Pad #
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
SSD 1851
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74
SSD 1850
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74
X-pos
2494.80 2430.00 2365.20 2300.40 2235.60 2170.80 2106.00 2041.20 1976.40 1911.60 1846.80 1782.00 1717.20 1652.40 1587.60 1522.80 1458.00 1393.20 1328.40 1263.60 1198.80 1134.00 1096.20 1004.40 939.60 874.80 810.00 745.20 680.40 615.60 550.80 486.00 421.20 356.40 291.60 226.80 162.00 97.20 32.40 -32.40 -97.20 -162.00 -226.80 -291.60 -356.40 -421.20 -486.00 -550.80 -615.60 -680.40
Y-pos
788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55
Pad #
251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
SSD 1851
SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124
SSD 1850
SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124
X-pos
-745.20 -810.00 -847.80 -939.60 -1004.40 -1069.20 -1134.00 -1198.80 -1263.60 -1328.40 -1393.20 -1458.00 -1522.80 -1587.60 -1652.40 -1717.20 -1782.00 -1846.80 -1911.60 -1976.40 -2041.20 -2106.00 -2170.80 -2235.60 -2300.40 -2365.20 -2430.00 -2494.80 -2559.60 -2624.40 -2689.20 -2754.00 -2818.80 -2883.60 -2948.40 -3013.20 -3078.00 -3142.80 -3207.60 -3272.40 -3337.20 -3402.00 3466.80 -3531.60 -3596.40 -3661.20 -3726.00 -3790.80 -3855.60 -3920.40
Y-pos
788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
9
Pad # 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347
SSD 1851
SEG125 SEG126 SEG127 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 N/C COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 ICONS N/C N/C
SSD 1850
SEG125 SEG126 SEG127 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 N/C COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 N/C N/C N/C N/C N/C N/C N/C N/C ICONS N/C N/C
X-pos -3985.20 -4050.00 -4114.80 -4179.60 -4244.40 -4309.20 -4374.00 -4438.80 -4503.60 -4568.40 -4633.20 -4698.00 -4762.80 -4827.60 -4892.40 -4957.20 -5022.00 -5086.80 -5151.60 -5216.40 -5281.20 -5346.00 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20 -5974.20
Y-pos 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 788.55 889.95 825.15 760.35 695.55 630.75 565.95 501.15 436.35 371.55 306.75 241.95 177.15 112.35 47.55 -17.25 -82.05 -146.85 -211.65 -276.45 -341.25 -406.05 -470.85 -535.65 -600.45 -898.05
y x
SSD1850/51
Pad 1 to 130
Bump Size PAD# 1 - 130 131 - 156 323 - 347 157 - 322
X [um] 52.2 75 75 45
Y [um] 60 45 45 75
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SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
PIN DESCRIPTIONS
RES This pin is reset signal input. When the pin is low, initialization of the chip is executed.
PS0, PS1
PS0 and PS1 determine the interface protocol between the driver and MCU. Refer to the following table for details. PS0 L L H H PS1 L H L H Interface 3-wire SPI (write only) 4-wire SPI (write only) 8080 parallel interface (read and write allowed) 6800 parallel interface (read and write allowed)
CS
This pin is chip select input. The chip is enabled for display data/command transfer only when CS is low.
D/ C
This input pin is to identify display data/command cycle. When the pin is high, the data written to the driver will be written into display RAM. When the pin is low, the data will be interpreted as command. This pin must be connected to VSS when 3-lines SPI interface is used.
R/W ( WR )
This pin is microprocessor interface signal. When 6800 interface mode is selected (by PS0 and PS1), the signal indicates read mode when high and write mode when low. When 8080 interface mode is selected (by PS0 and PS1), a data write operation is initiated when R/W( WR ) is low and the chip is selected.
E(RD )
This pin is microprocessor interface signal. When 6800 interface mode is selected (by PS0 and PS1), a data operation is initiated when E( RD ) is high and the chip is selected. When 8080 interface mode is selected (PS0 and PS1), a data read operation is initiated when E( RD ) is low and the chip is selected.
D0-D7
These pins are 8-bit bi-directional data/command bus to be connected to the microprocessor's data bus. When serial mode is selected, D7 is the serial data input SDA and D6 is the serial clock input SCK.
INTRS
This pin is an input pin to enable the internal resistor network for the voltage regulator when INTRS is high. When external regulator is used, this pin must be connected to VSS, and external resistor R1/R2 should be connected to VL6, VR and VSS.
REF
This pin is an input pin to enable the internal reference voltage used for the internal regulator. When it is high, an internal reference voltage source will be used. When it is low, an external reference voltage source must be provided to VEXT pin if internal regulator is used.
VDD
Power supply pin.
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
11
VSS
Ground.
VCI
Reference voltage input for internal DC-DC converter. The voltage of generated VCC equals to the multiple factor (2X, 3X, 4X, 5X or 6X) times VCI with respect to VSS. Note: voltage at this input pin must be larger than or equal to VDD. 6x is available for SSD1851 only.
VCC
This is the most positive voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC converter. When using internal DC-DC converter as generator, voltage at this pin is for internal reference only. It CANNOT be used for driving external circuitries.
C1P, C2P, C3P, C4P, C5P, C1N and C2N
When internal DC-DC voltage converter is used, external capacitor(s) is/are connected to these pins. (Reference to application Circuit on P.42)
VL6
This pin is the most positive LCD driving voltage. It can be supplied externally or generated by the internal regulator.
VR
This pin is an input of the internal voltage regulator. When the internal resistors network for the voltage regulator is disabled (INTRS is pulled low), external resistors should be connected between VSS and VR, and VR and VL6, respectively (Please refer to application circuit on P.43).
VEXT
This pin is an input to provide an external voltage reference for the internal voltage regulator when REF pin is pulled L.
VL5, VL4, VL3 and VL2
These are LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They have the following relationship: VL6 > VL5 > VL4 > VL3 > VL2 > VSS 1:a bias VL5 VL4 VL3 VL2 (a-1)/a*VL6 (a-2)/a*VL6 2/a*VL6 1/a*VL6
For SSD1851, "a" equals to 10 at POR. For SSD1850, "a" equals to 9 at POR.
COM0 - COM79
These pins provide the row driving signal COM0 - COM79 to the LCD panel.
ICONS
This pin is the special icon line COM signal output.
12
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
SEG0 - SEG127
These pins provide the LCD column driving signal. Their voltage level is VSS during sleep mode and standby mode.
S5150
For SSD1851, this pin must be connected to VSS. For SSD1850, this pin must be connected to VDD.
CL
This pin is the external clock input for the device if external clock mode is selected by software command. Under POR operation, this pin should be left opened and internal oscillator will be used after power on reset.
N/C
These No Connection pins should NOT be connected to any signal pins nor shorted together. They should be left open.
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
13
FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/ C pin. If D/ C is high, data is written to Graphic Display Data RAM (GDDRAM). If D/ C is low, the input at D0-D7 is interpreted as a Command and it will be decoded and written to the corresponding command register. Reset is of the same function as Power ON Reset (POR). Once RES receives a negative reset pulse of about 1us, all internal circuitry will be back to its initial status. Refer to Command Description section for more information.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D0-D7), R/W( WR ), D/ C , E( RD ) and CS . R/W( WR ) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. R/W( WR ) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/ C input. The E( RD ) and CS input serves as data latch signal (clock) when they are high and low respectively. Refer to P.35, Figure 1 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 4 below.
R/W( WR )
E( RD )
Data bus
N write column address dummy read
n data read1
n+1 data read 2
n+2 data read 3
Figure 4 - display data read with the insertion of dummy read MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D0-D7), R/W( WR ), E( RD ), D/ C and CS . The
CS input serves as data latch signal (clock) when it is low. Whether it is display data or status register
read is controlled by D/ C . R/W( WR ) and E( RD ) input indicate a write or read cycle when CS is low. Refer to P.37, Figure 2 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read.
14
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
MPU Serial 4-wire Interface
The serial interface consists of serial clock SCK, serial data SDA, D/ C and CS . Input to SDA is shifted into a 8-bit shift register on every rising edge of SCK in the order of D7, D6,...D0. D/ C is sampled on every eighth clock and the content in the shift register is written to the Display Data RAM or command register in the same clock. No extra clock or command is required to end the transmission.
MPU Serial 3-wire Interface
Operation is similar to 4-wire serial interface except D/ C is not used. The Set Display Data Length command is used to indicate that a specified number display data byte (1-256) is to be transmitted. Next byte after the display data string is handled as a command. It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in the serial communication, a hardware reset pulse at RES pin is required to initialize the chip for re-synchronization.
Modes of operation
Data Read Data Write Command Read Command Write 6800 parallel Yes Yes Status only Yes 8080 parallel Yes Yes Status only Yes Serial No Yes No Yes
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128 x 81 x 2 = 20736bits. Figure 5 is a description of the GDDRAM address map. For mechanical flexibility, remapping on both Segment and Common outputs are provided respectively. For vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the RAM data to be mapped to the display. Figure 5a and 5b show the cases in which the display start line register are set at 38H or 48H.
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
15
First Byte
Page address
Second Byte
Line address D0(LSB) D1 D2 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
D3 D2 D1 D0
COM Output (Display Startline = 0) COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
COM Output (Display Startline = 38H) COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
0
0
0
0
D3 D4 D5 D6 D7(MSB) D0(LSB) D1 D2
0
0
0
1
D3 D4 D5 D6 D7(MSB)
|
|
|
|
---------------------------------------------D0(LSB) D1 D2 ------------------------------------------------------------------------------------------------------------------------------------------------30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
0
1
1
0
D3 D4 D5 D6 D7(MSB) D0(LSB) D1 D2
0
1
1
1
D3 D4 D5 D6 D7(MSB)
1
0
0
0
D0
----------
ICONS
ICONS
ICONS
Internal Column Address ADC = 0 ADC = 1 SEG Outputs
00 00 7F
01
02 01 7E
03
04 02 7D
05
06 03 7C
07
F8 7C 03
F9
FA 7D 02
FB
FC 7E 01
FD
FE 7F 00
FF
Mapping depends on COM scan direction setting
SEG0
SEG1
SEG2
SEG3
SEG124
SEG125
SEG126
SEG127
Figure 5a. Graphic Display Data RAM (GDDRAM) Address Map for SSD1850 (with vertical scroll value 38H)
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SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
First Byte
Page address
Second Byte
D3 D2 D1 D0 D0(LSB) D1 D2 0 0 0 0 D3 D4 D5 D6 D7(MSB) D0(LSB) D1 D2 0 0 0 1 D3 D4 D5 D6 D7(MSB) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | | | ---------------------------------------------D0(LSB) D1 D2 1 0 0 0 D3 D4 D5 D6 D7(MSB) D0(LSB) D1 D2 1 0 0 1 D3 D4 D5 D6 D7(MSB) ------------------------------------------------------------------------------------------------------------------------------------------------40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Line address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
COM Output COM Output (Display (Display Startline = 0) Startline = 48H) COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79
COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
1
0
1
0
D0
----------
ICONS
ICONS
ICONS
Internal Column Address 00 ADC = 0 ADC = 1 SEG Outputs 00 7F
01
02 01 7E
03
04 02 7D
05
06 03 7C
07
F8 7C 03
F9
FA 7D 02
FB
FC 7E 01
FD
FE 7F 00
FF
Mapping depends on COM scan direction setting
SEG0
SEG1
SEG2
SEG3
SEG124
SEG125
SEG126
SEG127
Figure 5b. Graphic Display Data RAM (GDDRAM) Address Map for SSD1851 (with vertical scroll value 48H)
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
17
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 6). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.
Oscillator enable
enable Oscillation Circuit
enable Buffer
(CL)
Internal resistor Internal pwellresistor
OSC1 OSC2
Figure 6. Oscillator Circuitry
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage needed for display output. It takes a single supply input and generates necessary bias voltages. It consists of: 1. 2X, 3X, 4X, 5X and 6X DC-DC voltage converter *Note: SSD1850 works up to 5X only. Please refer to application notes on P.42. 2. Voltage Regulator Feedback gain control for initial LCD voltage. External resistors are connected between VSS and VR, and between VR and VL6. These resistors are chosen to give the desired VL6 according to the following equations:
R VL 6 = 1 + 2 * Vcon * G R1
63 - Vcon = 1 - * Vref 210
where Vref is the internally generated reference voltage with a known R1 and R2. Typical value for Vref is 2.1V R1 is the resistance of the resistor between VSS and VR. R2 is the resistance of the resistors between VR and VL6. is the software contrast level from 0 to 63. G = 1 if INTRS = VDD; REF = VDD G = 0.80 if INTRS = VSS; REF = VDD
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SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
3. Bias Divider If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (VL6) to give the LCD driving levels (VL2 -VL5). A low power consumption circuit design in this bias divider saves most of the display current comparing to traditional design. Stabilizing Capacitors (0.47~2uF) are required to be connected between these voltage level pins (VL2 VL5) and VSS. If the LCD panel loading is heavy, four additional resistors are suggested to add to the application circuit as following:
VSS
RL
VL2
VL3
VL4
RL
VL5
RL
VL6 Remarks: 1. C2 = 0.47~2.0uF 2. RL = 100K~1M (Optional)
+ C2
RL VSS
+ C2 + C2 + C2 + C2
Connections for heavy loading applications
4. Contrast Control Software control of 64 voltage levels of LCD voltage. 5. Bias Ratio Selection circuitry Software control of 1/4 to 1/10 bias ratio to match the characteristic of LCD panel. Note: SSD1850 has 1/4 to 1/9 bias only. 6. Self adjust temperature compensation circuitry Provide 2 different temperature compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Default temperature coefficient (TC) value is -0.05%/C.
193 / 209 Bit Latch
A register carries the display signal information. In 128X65/81 display mode, data will be fed to the HVbuffer Cell and level-shifted to the required level.
Level Selector
Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform.
HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter which translates the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal.
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
19
Reset Circuit
When RES input is low, the chip is initialized to the following: 1. Page address is set to 0 2. Column address is set to 0 3. Display is OFF 4. Display Start Line is set to 0 (GDDRAM page 0, D0) 5. Display Offset is set to 0 (COM0 is mapped to ROW0) 6. 128x80 display mode for SSD1851 and 128x64 display mode for SSD1850. 7. Normal/Reverse Display is Normal 8. N-line Inversion Register is 0 9. Entire Display is OFF 10. Power Control Register (VC, VR, VF) is set to (0,0,0) 11. 3X Booster is selected 12. Internal Resistor Ratio register is set to 0H 13. Software Contrast is set to 32 14. LCD Bias Ratio is set to 1/10 for SSD1851 and 1/9 for SSD1850. 15. Normal scan direction of COM outputs 16. Segment remap is disabled (SEG0 display column address 0) 17. Internal oscillator is OFF 18. Test mode is OFF 19. Temperature coefficient is set to PTC0 (-0.05%) 20. Icon display line is OFF When RESET command is issued, the following parameters are initialized only: 1. Page address is set to 0 2. Column address is set to 0 3. Initial Display Line is set to 0 (point to display RAM page 0, D0) 4. Internal Resistor Ratio register is set to 0H 5. Software Contrast is set to 32
20
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
LCD Panel Driving Waveform
The following is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms shown in Figure 7a and 7b illustrate the desired multiplex scheme with N-line Inversion feature is disabled (default).
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 01234 GGGGG EEEEE
* N 123456789 N ... *
Figure 7a. LCD Display Example "0"
TIME SLOT
1 2 3 4 5 6 7 89 * ...N 123456789 * ... N 1 2 3 4 5 6 7 8 9 ..
VL6 VL5 COM0 VL4 VL3 VL2 VSS VL6 VL5 COM1 VL4 VL3 VL2 VSS VL6 VL5 SEG0 VL4 VL3 VL2 VSS VL6 VL5 SEG1 VL4 VL3 VL2 VSS M
* Note: N is the number of multiplex ratio including Icon line. If it is enabled, N is equal to 80 for SSD1851 and 64 for SSD1850 on POR
Figure 7b. LCD Driving Signal From SSD1850/51
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
21
COMMAND TABLE
Hex
00~0F
D7
0
D6
0
D5
0
D4
0
D3
C3
D2
C2
D1
C1
D0
C0
Command
Description
Set Lower Column Address Set Upper Column Address Reserved
Set the lower nibble of the column address pointer for RAM access. The pointer is reset to 0 after rest. Set the upper nibble of the column address pointer for RAM access. The pointer is reset to 0 after rest. Reserved The internal regulator gain (1+R2/R1)Vcon increases as R2R1R0 is increased from 000b to 111b. The factor, 1+R2/R1, is given by: R2R1R0 = 000: 2.3 (POR) R2R1R0 = 001: 3.0 R2R1R0 = 010: 3.7 R2R1R0 = 011: 4.4 R2R1R0 = 100: 5.1 R2R1R0 = 101: 5.8 R2R1R0 = 110: 6.5 R2R1R0 = 111: 7.2 VC=0: turns OFF the internal voltage booster (POR) VC=1: turns ON the internal voltage booster VR=0: turns OFF the internal regulator (POR) VR=1: turns ON the internal regulator VF=0: turns OFF the output op-amp buffer (POR) VF=1: turns ON the output op-amp buffer Reserved The next command specifies the row address pointer (0-79) of the RAM data to be displayed in COM0. This command has no effect on ICONS. The pointer is set to 0 after reset. The next command specifies the mapping of first display line (COM0) to one of ROW0~79 (SSD1851) or (COM0) to one of ROW0~63 (SSD1850). This command has no effect on ICONS. COM0 is mapped to ROW0 after reset. The next command specifies the number of lines, excluding ICONS, to be displayed. With Icon is disabled (POR), duties 1/16~1/80 (SSD1851) or 1/16~1/64 (SSD1850) could be selected. With Icon enabled, the available duty ratios are 1/17~ 1/81 (SSD1851) or 1/17~1/65 (SSD1850). The next command sets the n-line inversion register from 3 to 33 lines to reduce display crosstalk. Register values from 00001b to 11111b are
SOLOMON
10~17
0
0
0
1
0
C6
C5
C4
18~1F 20~27 0 0 1 0 0 R2 R1 R0
Set Internal Regulator Resistor Ratio
28~2F
0
0
1
0
1
VC
VR
VF
Set Power Control Register
30~3F 40~43 0 X 1 L6 0 L5 0 L4 0 L3 0 L2 X L1 X L0
Reserved Set Display Start Line
44~47
0 X
1 C6
0 C5
0 C4
0 C3
1 C2
X C1
X C0
Set Display Offset
48~4B
0 X
1 D6
0 D5
0 D4
1 D3
0 D2
X D1
X D0
Set Multiplex Ratio
4C~4F
0 X
1 X
0 X
0 N4
1 N3
1 N2
X N1
X N0
Set N-line Inversion
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50~56
0
1
0
1
0
B2
B1
B0
Set LCD Bias
57~63 64~67 0 1 1 0 0 1 B1 B0
Reserved Set DC-DC Converter Factor
mapped to 3 lines to 33 lines respectively. Value 00000b disables the N-line inversion, which is the POR value. To avoid a fix polarity at some lines, it should be noted that the total number of mux (including the icon line) should NOT be a multiple of the lines of inversion (n). Sets the LCD bias from 1/4 ~ 1/10 according to B2B1B0: 000: 1/4 bias 001: 1/5 bias 010: 1/6 bias 011: 1/7bias 100: 1/8 bias 101: 1/9 bias (POR for SSD1850) 110: 1/9 bias (SSD1850); 1/10 bias (POR for SSD1851) Reserved Sets the DC-DC multiplying factor from 2X to 6X B1B0: 00: 2X/3X (POR, 2X or 3X multiplying depended on the DC-DC converter hardware configuration) 01: 4X 10: 5X 11: 5X (SSD1850); 6X (SSD1851) Reserved The next command sets one of the 64 contrast levels. The darkness increase as the contrast level increase. The level is set to 32 after POR. Set the desired VL6 voltage value: 0000: original contrast 0001: original contrast +1 step 0010: original contrast +2 steps 0011: original contrast +3 steps 0100: original contrast +4 steps 0101: original contrast +5 steps 0110: original contrast +6 steps 0111: original contrast +7 steps 1000: original contrast -8 steps 1001: original contrast -7 steps 1010: original contrast -6 steps 1011: original contrast -5 steps 1100: original contrast -4 steps 1101: original contrast -3 steps 1110: original contrast -2 steps 1111: original contrast -1 step Please refer the sequence of OTP programming Reserved Set gray scale mode and register. These are two-byte commands used to specify the contrast levels for the gray scale, 4 levels available. After power on reset,
68~80 81 1 X 0 X 0 C5 0 C4 0 C3 0 C2 0 C1 1 C0
Reserved Set Contrast Control Register OTP Setting
82
1 1
0 1
0 1
0 1
0 X3
0 X2
1 X1
0 X0
83
1
0
0
0
0
0
1
1
OTP Programming Reserved
84~87 88 1
WB3
0
WB2
0
WB1
0
WB0
1
WA3
0
WA2
0
WA1
0
WA0
Set White mode, nd st Frame 2 & 1 Set White mode, th rd Frame 4 & 3
89
1
WD3
0
WD2
0
WD1
0
WD0
1
WC3
0
WC2
0
WC1
1
WC0
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23
8A
1
LB3
0
LB2
0
LB1
0
LB0
1
LA3
0
LA2
1
LA1
0
LA0
Set Light Gray nd mode, Frame 2 st &1 Set Light Gray th mode, Frame 4 rd &3 Set Dark Gray nd mode, Frame 2 st &1 Set Dark Gray th mode, Frame 4 rd &3 Set Black mode, nd st Frame 2 & 1 Set Black mode, th rd Frame 4 & 3 Set PWM and FRC
8B
1
LD3
0
LD2
0
LD1
0
LD0
1
LC3
0
LC2
1
LC1
1
LC0
8C
1
DB3
0
DB2
0
DB1
0
DB0
1
DA3
1
DA2
0
DA1
0
DA0
WA0~3 = WB0~3 = WC0~3 = WD0~3 = 0000 LA0~3 = LB0~3 = LC0~3 = LD0~3 = 0000 DA0~3 = DB0~3 = DC0~3 = DD0~3 = 1111 BA0~3 = BB0~3 = BC0~3 = BD0~3 = 1111 Memory Content 1 Byte 0 0 1 1
st
8D
1
DD3
0
DD2
0
DD1
0
DD0
1
DC3
1
DC2
0
DC1
1
DC0
2
nd
Byte 0 1 0 1
Gray Mode White Light Gray Dark Gray Black
8E
1
BB3
0
BB2
0
BB1
0
BB0
1
BA3
1
BA2
1
BA1
0
BA0
8F
1
BD3
0
BD2
0
BD1
0
BD0
1
BC3
1
BC2
1
BC1
1
BC0
90~97
1
0
0
1
0
FR C
PW M1
PW M0
98~9F A0~A1 1 0 1 0 0 0 0 S0
Reserved Set Segment Remap Set Icon Enable
Sets PWM and FRC for gray-scale operation. FRC = 0 : 4-frame (POR) FRC = 1 : 3-frame PWM1 PWM0 = 00 & 01 : 9-levels (POR) PWM1 PWM0 = 10 : 12-levels PWM1 PWM0 = 11 : 15-levels Reserved S0=0: column address 00H is mapped to SEG0 (POR) S0=1: column address 7FH is mapped to SEG0 C0=0: Disable icon row (Mux = 16 to 80/64, POR) C0=1: Enable icon row (Mux = 17 to 81/65) E0=0: Normal display (display according to RAM contents, POR) E0=1: All pixels are ON regardless of the RAM contents *Note: This command will override the effect of "Set Normal/Inverse Display" R0=0: Normal display (display according to RAM contents, POR) R0=1: Inverse display (ON and OFF pixels are inverted) *Note: This command will not affect the display of the icon line S0=0: Standby mode (POR) S0=1: Sleep mode Reserved Oscillator is OFF, after reset, until this command is issued. Reserved D0=0: Display OFF (POR) D0=1: Display ON
A2~A3
1
0
1
0
0
0
1
C0
A4~A5
1
0
1
0
0
1
0
E0
Set Entire Display On/Off
A6~A7
1
0
1
0
0
1
1
R0
Set Normal/Inverse Display
A8~A9
1
0
1
0
1
0
0
S0
Set Power Save Mode Reserved
AA AB 1 0 1 0 1 0 1 1
Start Internal Oscillator Reserved
AC~AD AE~AF 1 0 1 0 1 1 1 D0
Set Display On/Off
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B0~BF
1
0
1
1
P3
P2
P1
P0
Set Page Address Set COM Output Scan Direction
C0~CF
1
1
0
0
S0
X
X
X
D0~E0 E1 1 1 1 0 0 0 0 1
Reserved Exit Power-save Mode Software Reset Reserved
1 1 1 0 0 1 0 0
Set GDDRAM page address (0~10) using P3P2P1P0 for RAM access. The page address is sets to 0 after reset. S0=0: Normal mode (POR) S0=1: Remapped mode. COM0 to COM[N-1] becomes COM[N-1] to COM0 when the duty is set to N. See Figure 5 as an example for N equals to 80. *Note: This command will not affect the display of the icon lines Reserved DC-DC converter, regulator and divider status before entering the power-save mode is restored. At POR, Power-save Mode is released. Initialize some internal registers Reserved The frame will be inverted once per frame Reserved This command is valid only at 3-wire SPI (PS0=PS1=L) The next command specifies the number of bytes of display data to be written after this composite command. D(7:0)=00: 1 byte of display data is to be sent D(7:0)=FF: 256 bytes of display data is to be sent Reserved Test mode commands and Extended features, see Extended Command Table.
E2 E3 E4
1
1
1
0
0
0
1
0
Exit N-line Inversion Reserved
E5~E7 E8 1 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0
Set Display Data Length
E9~EF F0~FF 1 1 1 1 X X X X
Reserved Extended Features
Extended Command Table
Bit Pattern Command Description
11110000 000000X1X0
X1X0 : Set VL6 noise reduction
11110001 00001X2X1X0 11110111 0000000X0 11110010 00000X2X1X0
X2X1X0 : Set TC Value Select Oscillator Source
Oscillator Adjustment
X1X0 = 00: Enable (POR) X1X0 = 11: Normal Remarks: This command is only valid for the IC version with G prefix notation on the "DTE" (datecode) field of label printed on die tray cover, intermediates and outer boxes. X2X1X0 = 000: -0.05%/C (POR) X2X1X0 = 001: -0.07%/C X0 = 0: Internal RC oscillator is selected (POR) X0 = 1: External oscillator from CL pin is selected X2X1X0 = 000: -9% X2X1X0 = 001: -6% X2X1X0 = 010: -3% X2X1X0 = 011: 0 (POR) X2X1X0 = 100: +3%
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25
11111101 xxxx0X210
Lock / Unlock Interface
11110110 000X4X3X2X1X0
Frame Frequency Adjust (Please find the default setting in the following table)
Other than the above
Set Test Mode
X2X1X0 = 101: +6% X2X1X0 = 110: +9% X2X1X0 = 111: +12% X2 = 0 : Unlock the IC. The driver accepts any command and data written. X2 = 1 : Lock the IC. The driver ignores all command and data written, except the unlock command or pin reset. FRAMEFQ X2X1X0 = 000: 0 X2X1X0 = 001: 1 X2X1X0 = 010: 2 X2X1X0 = 011: 3 X2X1X0 = 100: 4 X2X1X0 = 101: 5 X2X1X0 = 110: 6 X2X1X0 = 111: 7 Fosc X4X3 = 00: 59kHz X4X3 = 01: 75kHz X4X3 = 10: 94kHz X4X3 = 11: 113kHz Reserved
Frame Frequency Default Setting
Frame Frequency = Fosc / [Mux x (FRAMEFQ + 1) x PWM]
Mux (Icon Enable) Mux<=17
18<=MUX<=33 34<=MUX<=49 50<=MUX<=65 66<=MUX<=81
FRAMEFQ 2 5 4 1 1 2 0 1 1 0 0 1 0 0 0
PWM 15 12 9 15 12 9 15 12 9 15 12 9 15 12 9
Fosc 59kHz 94kHz 59kHz 75kHz 59kHz 75kHz 59kHz 94kHz 75kHz 75kHz 59kHz 94kHz 94kHz 75kHz 59kHz
PWM is defined in command Set PWM and FRC.
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Read Status Byte
A 8 bits status byte will be placed onto the data bus when a read operation is performed if D/ C is low. The status byte is defined as following: D7 D6 D5 D4 D3 D2 D1 D0 Comment BUSY ON 0 1 0 DS1 DS0 BUSY=0 : Chip is idle RES BUSY=1 : Chip is executing instruction ON=0 : Display is OFF ON=1 : Display is ON RES =0: Chip is idle
RES =1: Chip is executing reset DS1, DS0 = 00: SSD1850 DS1, DS0 = 01: SSD1851
Data Read / Write
To read data from the GDDRAM, input High to R/W( WR ) pin and D/ C pin for 6800-series parallel mode, Low to E( RD ) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided for serial mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a dummy read is required before the first data is read. See P.14, Figure 4 in Functional Description. To write data to the GDDRAM, input Low to R/W( WR ) pin and High to D/ C pin for 6800-series parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. After the data read/write operation (address=127) is executed, the address will be reset to 0 in next data read/write operation.
Address Increment Table (Automatic)
D/ C 0 0 1 1 R/W( WR ) 0 1 0 1 Action Write Command Read Status Write Data Read Data Auto Address Increment No No Yes Yes
Address Increment is done automatically after data read/write. The column address pointer of GDDRAM is affected. After the data read/write operation (address=127) is executed, the address will be reset to 0 in next data read/write operation.
Commands Required for R/W ( WR ) Actions on RAM
R/W ( WR ) Actions on RAMs
Read/Write Data from/to GDDRAM.
Commands Required
Set GDDRAM Page Address Set GDDRAM Column Address (1011X3X2X1X0)* (0001X3X2X1X0)* (0000X3X2X1X0)* (X7X6X5X4X3X2X1X0)
Read/Write Data * No need to resend the command again if it is set previously. The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content whether the target RAM content is being displayed or not.
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27
COMMAND DESCRIPTIONS
Set Display On/Off
This command turns the display on/off, by the value of the LSB.
Set Display Start Line
This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63/79. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0. The display start line values of 0 to 63/79 are assigned to Page 0 to 9.
Set Page Address
This command positions the page address to 0 to 8/10 possible positions in GDDRAM. Refer to figure 5. Set Higher Column Address This command specifies the higher nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>127).
Set Lower Column Address
This command specifies the lower nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>127).
Set Segment Re-map
This commands changes the mapping between the display data column address and segment driver. It allows flexibility in layout during LCD module assembly. Refer to figure 5.
Set Normal/Inverse Display
This command sets the display to be either normal/inverse. In normal display, a RAM data of 1 indicates an "ON" pixel. While in reverse display, a RAM data of 0 indicates an "ON" pixel. The icon line is not affected by this command.
Set Entire Display On/Off
This command forces the entire display, including the icon row, to be "ON" regardless of the contents of the display data RAM. This command has priority over normal/inverse display. To execute this command, Set Display On command must be sent in advance.
Set LCD Bias
This command is used to select a suitable bias ratio (1/4 to 1/11) required for driving the particular LCD panel in use. The POR default for SSD1851 is set to 1/10 bias and SSD1850 is set to 1/9.
Software Reset
This command causes some of the internal status of the chip to be initialized: 1. Page address is set to 0 2. Column address is set to 0 3. Initial Display Line is set to 0 (point to display RAM page 0, D0) 4. Internal Resistor Ratio register is set to (0,0,0) 5. Software Contrast is set to 32
Set COM Output Scan Direction
This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly.
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Set Power Control Register
This command turns on/off the various power circuits associated with the chip.
Set Internal Regulator Resistors Ratio
This command is to enable any one of the eight internal resistor (IRS) settings for different regulator gains when using internal regulator resistor network (INTRS pin pulled high). The Contrast Control Voltage Range curves is given in the figure below:
Set Contrast Control Register
This command adjusts the contrast of the LCD panel by changing VL6 of the LCD drive voltage provided by the On-Chip power circuits. VL6 is set with 64 steps (6-bit) contrast control register. It is a compound commands:
Set Contrast Control Register Contrast Level Data No Changes Complete? Yes
Set Display Offset
The next command specifies the mapping of display start line (COM0 if display start line register equals to 0) to one of ROW0-79. This command has no effect on ICONS. COM0 is mapped to ROW0 after reset.
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29
Set Multiplex Ratio
This command switches default 80 multiplex mode to any multiplex from 16 to 80, if Icon is disabled (POR). When Icon is set enable, the corresponding multiplex ratio setting will be mapped to 17 to 81. The chip pads ROW0-ROW79 will be switched to corresponding COM signal output.
Set Power Save Mode
This command forces the chip to enter Standby or Sleep Mode. LSB of the command will define which mode will be entered.
Exit Power Save Mode
This command releases the chip from either Standby or Sleep Mode and return to normal operation.
Set N-line Inversion
Number of line inversion is set by this command for reducing crosstalk. 3 to 33-line inversion operations could be selected. At POR, this operation is disabled. It should be noted that the total number of mux (including the icon line) should NOT be a multiple of the inversion number (N). Or else, some lines will not be changed their polarity during frame change.
Exit N-line Inversion
This command releases the chip from N-line inversion mode. The driving waveform will be inverted once per frame after issuing this command.
Set DC-DC Converter Factor
Internal DC-DC converter factor is set by this command. For SSD1850, 2X to 5X multiplying factors could be selected. 2X/3X, 4X, 5X and 6X factors are selected using this command. Hardware configuration is used for 2X or 3X setup. For SSD1851, 2X to 6X multiplying factors could be selected.
Set Icon Enable
This command enable/disable the Icon display.
Start Internal Oscillator
After POR, the internal oscillator is OFF. It should be turned ON by sending this command to the chip.
Set Display Data Length
This two-byte command only valid when 3-wire SPI configuration is set by H/W input (PS0=PS1=L). The second 8-bit is used to indicate that a specified number display data byte (1-256) are to be transmitted. Next byte after the display data string is handled as a command.
Set Gray Scale Mode (White/Light Gray/Dark Gray/Black)
Command 88(hex) to 8F(hex) are used to specify the four gray levels' pulse width at the four possible frames. The four gray levels are called white, light gray, dark gray and black. Each level is defined by 4 st registers for 4 consecutive frames. For example, WA is a 4-bit register to define the pulse width of the 1 nd frame in White mode. WB is a register for 2 frame in White mode etc. Each command specifies two registers.
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For 4 FRC,
Memory Content st nd 1 Byte 2 Byte 0 0 1 1 0 1 0 1 Gray Mode White Light Gray Dark Gray Black FRAME 1
st
2
nd
3
rd
4
th
WA LA DA BA
WB LB DB BB
WC LC DC BC
WD LD DD BD
For 3 FRC,
Memory Content st nd 1 Byte 2 Byte 0 0 1 1 0 1 0 1 Gray Mode White Light Gray Dark Gray Black FRAME 1
st
2
nd
3
rd
4 (No use) WD (XX) LD (XX) DC (XX) BC (XX)
th
WA LA DA BA
WB LB DB BB
WC LC DC BC
Set PWM and FRC
This command selects the number of frames in frame rate control, or the number of levels in the pulse width modulation.
Set Test Mode
This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, user should NOT use this command.
Status Register Read
This command is issued by setting D/ C Low during a data read (refer to figure 1 and 2 parallel interface waveform, P.35-38). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode.
EXTENDED COMMANDS
These commands are used, in addition to basic commands, to trigger the enhanced features designed for the chip. These features are on top of general ones.
Set VL6 noise reduction
This command is to enable the VL6 noise reduction. This command is only valid for the IC version with G prefix notation on the "DTE" (datecode) field of label printed on die tray cover, intermediates and outer boxes. For details, please refer to the product change notification document of PC0010 from SSL.
Set Temperature Coefficient (TC) Value
This command is to set 1 out of 2 different temperature coefficients in order to match various liquid crystal temperature grades.
Select Oscillator Source
This command enables the external clock input from CL pin.
Oscillator adjustment
This command is used to adjust the oscillator frequency to desired frame frequency.
Lock/Unlock Interface
After sending the lock command, the interface will be disabled until the unlock command is received. The lock command is suggested whenever the LCD driver will not be accessed for some period. This can minimize incorrect data or command written due to noisy interface.
SSD1850/51 Series Rev 1.2 01/2003 SOLOMON
31
MAXIMUM RATINGS
Symbol VDD VCC VCI Vin I TA Tstg Parameter Supply voltage Booster Supply Voltage Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Range Value -0.3 to 4.0 VSS-0.3 to VSS+18.0 VDD to 4.0 VSS-0.3 to VDD+0.3 25 -40 to +80 -65 to +150 Unit V V V V mA
o o
C C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS < or = (Vin or VOUT) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, VDD=1.8 to 3.3V, TA=-40 to 85C; unless otherwise specified.)
Symbol
VDD
Parameter
Logic Circuit Supply Voltage Range Voltage Generator Circuit Supply Voltage Range Access Mode Supply Current Drain (VDD Pins)
Test Condition
(Absolute value referenced to VSS)
Min
1.8
Typ (at 25C)
2.7
Max
3.3
Unit
V
IAC
VDD = 2.7V, Voltage Generator On, 4X Converter Enabled, Write accessing, Tcyc = 3.3MHz, Osc. Freq.=31kHz, Display On. VDD = 2.7V, VCC = 10.8V, Voltage Generator Off, Divider Enabled, Read/Write Halt, Osc. Freq.=31kHz, Display On, VL6=9V VDD = 2.7V, Vcc=10.8V, Voltage Generator On, 4x DC-DC Converter Enabled Divider Enabled, Read/Write Halt, Osc. Freq.=31kHz, Display On, VL6 = 9V. VDD = 2.7V, LCD Driving Waveform Off, Osc. Freq. 31KHz, Read/Write halt. VDD = 2.7V, LCD Driving Waveform Off, Oscillator Off, Read/Write halt. Display On, Voltage Generator Enabled, DC/DC Converter Enabled, Osc. Freq. = 31kHz, Regulator Enabled, Divider Enabled. ICC < 20uA Voltage Generator Disabled.
-
750
800
IDP1
Display Mode Supply Current Drain (VDD Pins)
-
40
60
IDP2
Display Mode Supply Current Drain (VDD Pins)
-
200
500
A
ISB
Standby Mode Supply Current Drain (VDD Pins) Sleep Mode Supply Current Drain (VDD Pins) LCD Driving Voltage Generator Output (VCC Pin)
-
27
40
A A V
ISLEEP VCC
VDD
0.5 -
2.5 15.0
DC-DC Converter Efficiency VLCD LCD Driving Voltage Input (VCCPin)
95 4.0
99 15.0
% V
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Symbol
VREF
Parameter
External Reference Voltage Input
Test Condition
Internal Reference Voltage Source Disable (REF pin pulled Low), External Reference voltage input to VEXT pin. Internal Reference Voltage Source Enabled (REF pin pulled High), VEXT pin NC. Iout = +500 Iout = -500 Regulator Enabled (VL6 voltage depends on Int/Ext Contrast Control) Regulator Disable
Min
2.04
Typ
2.10
Max
2.16
Unit
V
Internal Reference Voltage VOH1 VOL1 VL6 VL6 VIH1 VIL1 VL6 VL5 VL4 VL3 VL2 VL6 VL5 VL4 VL3 VL2 IOH IOL IOZ IIL/IIH Output High voltage (D0-D7) Output Low Voltage (D0-D7) LCD Driving Voltage Source (VL6 Pin) LCD Driving Voltage Source (VL6 Pin) Input high voltage (RES#, PS0, PS1, CS, D/C#, R/W#, D0-D7, REF, INTRS) Input Low voltage (RES#, PS0, PS1, CS, D/C#, R/W#, D0-D7, REF, INTRS) LCD Display Voltage Output (VL6, VL5, VL4, VL3, VL2 Pins)
2.10 0.8*VDD 0.0 VDD 0.8*VDD 0.0 Floating VL6 (a-1)/a*VL6 (a-2)/a*VL6 2/a*VL6 1/a*VL6 VDD 0.2*VDD VCC-0.5 VDD 0.2*VDD VCC VL6 VL5 VL4 VL3 -50 1 1
V V V V V V V V V V V V V V V V V A A A A
Divider Enabled, 1:a bias ratio, a=4~10 for SSD1851 and a =4~9 for SSD1850.
VL5 VL4 VL3 VL2 VSS 50 -1 -1
LCD Display Voltage Input (VL6, VL5, VL4, VL3, VL2 Pins)
Voltage reference to VSS, External Voltage Generator, Divider Disabled
Output High Current Source(D0-D7) Output Low Current Drain (D0-D7) Output Tri-state Current Drain Source (D0-D7) Input Current (RES#, PS0, PS1,CS#, E(RD#), D/C#,R/W#(WR#), D0~D7, REF, INTRS) Input Capacitance (all logic pins) Variation of VL6 Output (1.8V < VDD < 3.3V) Temperature Coefficient Compensation Temperature Coefficient [POR] Temperature Coefficient
Vout=VDD-0.4V Vout=0.4V
CIN VL6
5 Regulator Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 0 Voltage Regulator Enabled Voltage Regulator Enabled 2
7.5 -
pF %
PTC0 PTC1
-0.04 -0.06
-0.05 -0.07
-0.06 -0.08
% %
*The formula for the temperature coefficient is:
0 0 Vref at50 C - Vref at 0 C 1 TC (% / C ) = * *100% 0 0 0 50 C - 0 C Vref at 25 C 0
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33
AC ELECTRICAL CHARACTERISTICS
(TA=-40 to 85C, Voltages referenced to VSS, VDD=VCI=2.7V, unless otherwise specified.)
Symbol FFRM Parameter Frame Frequency (SSD1851) Fosc / [Mux x (FRAMEFQ+1) x PWM] Frame Frequency (SSD1850) Fosc / [Mux x (FRAMEFQ+1) x PWM] Test Condition Display ON, Set 128 x 81 Graphic Display Mode, Icon Line Enabled, 15PWM, Default frame frequency setting Display ON, Set 128 x 65 Graphic Display Mode, Icon Line Enabled, 15PWM, Default frame frequency setting Min 70 Typ (at 25C) 77.4 Max 100 Unit Hz
FFRM
70
76.9
100
Hz
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TABLE 3a. Parallel Timing Characteristics (TA=-40 to 85C, VDD=2.7V, VSS=0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 10 2 10 95 40 15 30 30 Typ Max 30 80 25 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns
R/ W
D/ C
tAS E t cycle
tAH
PW CSL CS tF tDSW D0 -D7 (Write data to driv er) tACC D 0-D 7 (Read data f rom driv er) Valid Data
PW CSH
tR tDHW
t DHR Valid Data tOH
Figure 1a. Parallel 6800-series Interface Timing Characteristics (PS0=H, PS1=H)
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
35
TABLE 3b. Parallel Timing Characteristics (TA=-40 to 85C, VDD=1.8V,VSS=0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 15 5 15 120 55 20 40 40 Typ Max 40 100 35 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns
R/ W
D/ C
tAS E t cycle
tAH
PW CSL CS tF tDSW D0 -D7 (Write data to driv er) tACC D 0-D 7 (Read data f rom driv er) Valid Data
PW CSH
tR tDHW
t DHR Valid Data tOH
Figure 1b. Parallel 6800-series Interface Timing Characteristics (PS0=H, PS1=H)
36
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
TABLE 4a. Parallel Timing Characteristics (TA=-40 to 85C, VDD=2.7V,VSS=0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 10 2 10 95 40 15 30 30 Typ Max 30 80 25 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns
D/C tAH
tAS
WR (R/W)
RD (E) tcycl e
PWCSL CS tF tD SW D0-D7 (Write dat a to driver) tAC C D0 -D7 (Read data from driver) Valid Data
PW CSH
tR t DH W
t D HR Valid Data tOH
Figure 2a. Parallel 8080-series Interface Timing Characteristics (PS0=H, PS1=L)
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
37
TABLE 4b. Parallel Timing Characteristics (TA=-40 to 85C, VDD=1.8V,VSS=0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 15 5 15 120 55 20 40 40 Typ Max 40 100 35 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns
D/C tAH
tAS
WR (R/W)
RD (E) tcycl e
PWCSL CS tF tD SW D0-D7 (Write dat a to driver) tAC C D0 -D7 (Read data from driver) Valid Data
PW CSH
tR t DH W
t D HR Valid Data tOH
Figure 2b. Parallel 8080-series Interface Timing Characteristics (PS0=H, PS1=L)
38
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
TABLE 5a. Serial Timing Characteristics (TA = -40 to 85C, VDD = 2.7V, VSS =0V)
Symbol Parameter Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time
tcycle tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH tR tF
Min 66 10 5 10 5 10 10 10 20 -
Typ -
Max 10 10
Unit ns ns ns ns ns ns ns ns ns ns ns
D/C (Required if PS1 = H) tAS CS tCSS t c ycle tC L KH tAH tCS H
tC LK L SCK tF tDSW SDA Valid Data
tR tDHW
CS
SCK
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3a. Serial Timing Characteristics (PS0=L)
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
39
TABLE 5b. Serial Timing Characteristics (TA = -40 to 85C, VDD = 1.8V, VSS =0V)
Symbol Parameter Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time
tcycle tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH tR tF
Min 70 15 10 15 10 15 15 15 30 -
Typ -
Max 10 10
Unit ns ns ns ns ns ns ns ns ns ns ns
D/C (Required if PS1 = H) tAS CS tCSS t c ycle tC L KH tAH tCS H
tC LK L SCK tF tDSW SDA Valid Data
tR tDHW
CS
SCK
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3b. Serial Timing Characteristics (PS0=L)
40
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
APPLICATION CIRCUIT
ICONS COM0 : : : : COM38 COM39
DISPLAY PANEL SIZE 128 X 80 + 1 ICON LINE
COM40 COM41 : : : : COM79
Remapped COM SCAN Direction [Command: C8]
Remapped COM SCAN Direction [Command: C8
SEG0..............................................................SEG127
Segment Remapped [Command: A1) SEG127.................................................................................SEG0
: : : : COM41 COM40
: : : : : COM0
SSD1851 DIE
81 MUX (DIE FACE IP) CS# D0-D7 INTRS REF E R/W D/C PS1 PS0 RES#
COM79 ICONS
: : : : : : COM38 COM39
Remapped COM SCAN Direction [Command: C8
Remapped COM SCAN Direction [Command: C8
C6P C4P C2P C1P C1N C3P C5P Vcc
VR VL6 VL4 VL5 VL3 VL2
CONTOL CIRCUIT
REGULATOR DIVIDER CIRCUIT
BOOSTER CIRCUIT
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
41
Application Circuit: DC-DC Converter Circuit Configuration
SSD1850/51 IC works from 2X to 6X DC-DC converter. For the capacitor connections, please refer to below circuit diagrams. Note that if the capacitor connection does not match with the software setting of DC-DC Converter Factor (0x64~0x67), abnormal current consumption will be observed.
Vss Vcc C5P C3P C1N C1P C2P C2N C4P
+ +
Vss Vcc C5P C3P C1N C1P C2P C2N C4P
+ + + -
2X Converter
3X Converter
Vss VCC C5P C3P C1N C1P C2P C2N C4P
+ + + + -
Vss VCC C5P C3P C1N C1P C2P C2N C4P
+ + + + +
4X Converter
5X Converter
+ + + + 6X Converter
Vss VCC C5P C3P C1N C1P C2P C2N C4P
+ + -
*Note: Capacitor value = 1.0uF to 4.7uF *Note: SSD1850 works up to 5X only.
42
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
Application Circuit: Regulator Circuit and Bias Divider Circuit Internal Regulator and Bias Divider
[COMMAND: 2F]
VL6 VL5 VL4 VL3 VL2
VSS
Capacitor = 0.47uF - 2.0uF
Remarks: INTRS = `H'
External Regulator and Internal Bias Divider
[COMMAND: 2D]
VR
Capacitor = 0.47uF - 2.0uF
VL6 VL5 VL4 VL3 VL2
VSS Remarks: INTRS = `L'
External Regulator Bias Divider
[COMMAND: 28]
VCC VL6 VL5 VL4 VL3 VL2
External VCC
VSS
Remarks: INTRS = `L'
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
43
OTP Programming Circuit and Sequence
OTP (One Time Programming) is a method to adjust the VL6. In order to eliminate the variations of LCD module in term of contrast level, OTP can be used to achieve the best contrast of every LCD modules. OTP setting and programming should include two major steps of (1) Find the OTP offset and (2) OTP programming as following,
Step 1. Find the OTP offset
(1) (2) (3) (4) (5) Hardware Reset (sending an active low reset pulse to RES pin) Send original initialization routines Set and display any test patterns Adjust the contrast value (0x81, 0x00~0x3F) until there is the best visual contrast OTP setting steps = Contrast value of the best visual contrast - Contrast value of original initialization
Example 1: Contrast value of original initialization = 0x20 Contrast value of the best visual contrast = 0x24 OTP setting steps = 0x24 - 0x20 = +4 OTP setting commands should be (0x82, 0xF4) Example 2: Contrast value of original initialization = 0x20 Contrast value of the best visual contrast = 0x1B OTP setting steps = 0x1B - 0x20 = -5 OTP setting commands should be (0x82, 0xFB)
Step 2. OTP programming
(6) Hardware Reset (sending an active low reset pulse to RES pin) (7) Enable Oscillator (0xAB) (8) Connect an external VCC (see diagram below) (9) Send OTP setting commands that we find in step 1 (0x82, 0xF0~0xFF) (10)Send OTP programming command (0x83) (11)Wait at least 2 seconds (12)Hardware Reset Verify the result by repeating step 1. (2) - (3)
SSD1850/51 (8)
R
VCC
+C
GND (1) & (6) & (12) GND
16-18V
RES
Note: R = 1K ~ 10k ohm C = 1u ~ 4.7u F
OTP Programming Circuit
44
SSD1850/51 Series Rev 1.2 01/2003 SOLOMON
Flow Chart of OTP Program
Start
Step 1 Step 2
(i) Hardware reset (ii) Send original initialization routines (iii) Set and display any test patterns
i) Hardware reset ii) Enable oscillator
Adjust the contrast level to the best visual level
Connect an external voltage (16-18V) on Vcc pins
Accept the contrast level on panel?
No
(i) Send OTP setting commands (ii) Send OTP programming command (iii) Wait > 2 sec (iv) Hardware reset
Yes
OTP setting step = Adjusted contrast value - Original contrast value
i) Send original initialization routines ii) Set and display any test patterns iii) Inspect the contrast
END
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
45
OTP Example program Find the OTP offset: 1. 2. Hardware reset by sending an active low reset pulse to RES pin COMMAND(0XAB) COMMAND(0X2F) 3. COMMAND(0X48) COMMAND(0X40) COMMAND(0X55) 4. COMMAND(0X81) COMMAND(0X2D) COMMAND(0X24) 5. COMMAND(0XB0) COMMAND(0x00) COMMAND(0X10) DATA(...) COMMAND(0XAF) 6. 7. 8. 9. OTP programming: Hardware reset by sending an active low reset pulse to RES pin COMMAND(0XAB) \\ Enable Oscillator \\ Set OTP offset value to +3 (0011) \\ 0001 X3X2X1X0 , where X3X2X1X0 is the OTP offset value \\ Send the OTP programming command Connect an external VCC (16V-18V) COMMAND(0XF3) 11. COMMAND(0X83) \\Enable oscillator \\ turn on the internal voltage booster, internal regulator and output op-amp buffer; Select booster level \\ Set Duty ratio \\ 64Mux \\ Set Biasing ratio (1/9 BIAS) \\ Set target gain and contrast. \\ contrast = 45 \\ gain = 5.1 \\ set page address \\ set lower nibble column address \\ set higher nibble column address \\ write target content to GDDRAM \\ Set Display On
\\ Set target display contents
OTP offset calculation... target OTP offset value is +3
10. COMMAND(0X82)
12. Wait at least 2 seconds for programming wait time 13. Hardware reset by sending an active low reset pulse to RES pin Verify the result: 14. After OTP programming, procedure 2 to 5 are repeated for inspection of the contrast on the panel
46
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
SSD1851T TAB PACKAGE DIMENSION (1 OF 3)
DO NOT SCALE THIS DRAWING
SO LO M ON
1T 85 D1 SS
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
47
SSD1851T TAB PACKAGE DIMENSION (2 OF 3)
DO NOT SCALE THIS DRAWING
48
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
SSD1851T TAB PACKAGE DIMENSION (3 OF 3)
DO NOT SCALE THIS DRAWING
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
49
SSD1851U COF PACKAGE DIMENSION (1 OF 2)
DO NOT SCALE THIS DRAWING
50
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
SSD1851U COF PACKAGE DIMENSION (2 OF 2)
DO NOT SCALE THIS DRAWING
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON
51
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
52
SSD1850/51 Series
Rev 1.2 01/2003
SOLOMON

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